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? semiconductor components industries, llc, 201 6 1 publication order number: june 2016 - rev. 0 lv8 811 g_lv8813g_lv8814j/d lv8 8 1 1g , lv8813g , lv8814j motor driver , 3 - phase, pwm, full - wave, bldc overview the lv8811g , lv8813g , and lv8814j are 3 - phase bldc m otor driver s which are controlled with single hall sensor. a 180 degrees sinusoidal driving method is adopted and the ic can control motor with low vibration and the low noise. l ead - angle adjustment is possible by external pin s . the l ead - angle base and lead - angle sl ope can be adjust ed independen tly . thus, the device can be driven by high efficiency and low noise with various motors. the power element to drive a motor is built - in and contributes to high efficiency by low on resistance (0.5 ). the hall sensor bias drive r is equipped , and a h all ic is support ed as well . as a method of the rotary speed control of the motor, direct - pwm pulse input or dc - voltage input can be chosen. features ? 3 - phase full wave (sinusoidal) drive ? a ny practical combination of slot and pole can be handled. (e.g. 3s 2 p, 3s4p , 6s4p, 6s8p, 12s8p, 9s12p and so on) ? b uilt - in power fets (p - mos/n - mos) ? speed control function by direct pwm or dc voltage input ? minimum input pwm duty cycle can be configured by voltage input ? soft start - up function and soft shutdown function ? soft pwm duty cycle transitions ? built - in current limit circuit and thermal protection circuit ? regulated voltage output pin for hall sensor bias ? built - in locked rotor protection and auto recovery circuit ? fg signal output ? dynamic lead angle adjustment with respect to rotational speed ? lead - angle control parameters can be configured by voltage input s . typical applications ? refrigerator ? pc ? games www . onsemi.com lv8811g, lv8813g : 20 - pin tssop w ith exposed pad case 948az lv8814j: 20 - pin ssop case 565an marking diagram xxxx = specific device code y = year m = month ddd = additional traceability data ordering information ordering code: lv8811g - ah lv8813g - ah lv8 814j - ah package lv8811g, lv8813g tssop20j (pb - free / halogen free) lv8814j ssop20 (pb - free / halogen free) shipping (qty / packing) 2 000 / tape & reel ? for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. http://www.onsemi.com/pub_link/collateral/brd8011 - d.pdf
lv8811g , lv8813g , lv8814j www. onsemi.com 2 block diagram figure 1 . lv8811g, lv8813g , and lv8814j block diagram
lv8811g , lv8813g , lv8814j www. onsemi.com 3 application circuit diagram 1 2 20 13 14 12 11 15 16 17 18 19 10 9 8 7 6 5 4 3 vo uo rf rfs vcc reg ph1 ph2 pwm fg pgnd (nc) wo sgnd cpwm vth mds in1 in2 hb ( ) ( ) r1 r11 r12 c 3 d1 c2 r 3 r4 r5 r6 r7 r8 r10 r9 r2 c1 cm zd1 pwm signal input rotation signal output power supply pull up power uo vo wo hall hall exposed - pad notice: lv8814j do not include the exposed - pad. figure 2 . three - phase bldc motor drive with lv8811g, lv8813g , and lv8814j using one hall sensor
lv8811g , lv8813g , lv8814j www. onsemi.com 4 1 2 20 13 14 12 11 15 16 17 18 19 10 9 8 7 6 5 4 3 vo uo rf rfs vcc reg ph1 ph2 pwm fg pgnd (nc) wo sgnd cpwm vth mds in 1 in2 hb ( ) ( ) r1 r11 r12 c3 hall ic d1 c2 r3 r 4 r5 r6 r 7 r8 r10 r9 r2 c1 cm zd1 pwm signal input rotation signal output power supply pull up power uo vo wo hall r 13 r14 r15 exposed - pad notice: lv8814j do not include the exposed - pad. figure 3 . three - phase bldc motor drive with lv8811g, lv8813g , and lv8814j using one hall ic
lv8811g , lv8813g , lv8814j www. onsemi.com 5 d1 1 2 20 13 14 12 11 15 16 17 18 19 10 9 8 7 6 5 4 3 vo uo rf rfs vcc reg ph1 ph2 pwm fg pgnd (nc) wo sgnd cpwm vth mds in1 in2 hb ( ) r1 r11 r12 c3 hall c2 r3 r4 r5 r6 r10 r 9 r2 c1 cm zd1 rotation signal output power supply pull up power c4 c5 r13 r14 r15 r16 mn1 r17 pwm signal input uo vo wo hall r18 exposed - pad notice: lv8814j do not include the exposed - pad. figure 4 . three - phase bldc motor drive with lv8811g, lv8813g, and lv881 4j using input pwm to dc conversion for speed control
lv8811g , lv8813g , lv8814j www. onsemi.com 6 e xample component value device v alue device v alue d1 mbra340t3g (o n semi) r5 0 to 50k zd1 mnsz5247bt1g (o n semi) r6 50 k to 0 r7 1k cm 4.7 f r8 nc c1 1500pf r9 1 k to 10 k c2 1 f r10 1k c3 0.1 f r11 0 to 50k c4 1 f r12 50 k to 0 c5 3 3 0pf r13 10k r14 30k r1 0.22 // 0.22 (0.5w) r15 7.5k r2 1k r16 62k r3 0 to 50k r17 68k r4 50 k to 0 r18 1 k
lv8811g , lv8813g , lv8814j www. onsemi.com 7 pin assignment figure 5 . lv8811g, lv8813g , and lv8814j pin assignment 1 vo 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 uo rf rfs vcc reg ph1 ph2 pwm fg in1 hb in2 mds vth cpwm sgnd wo (nc) pgnd exposed - pad notice: lv8814j do not include the exposed - pad.
lv8811g , lv8813g , lv8814j www. onsemi.com 8 lv8811 g , lv8813g , and lv8814j comparision assume application - lv 8811g : wide operation supply voltage range. suitable rotate for s mall - size f ans. - lv8813g: stable start - up even with a large load. suitable rotate for large - size fans. - lv8814j : stable start - up even with a large load. suitable rotate for large - size fan s . different c haracteristic s lv8811g lv8813g lv8814j comment reference page vcc/rf operating supply voltage range 3.6v to 16v 6.0v to 16v 3.6v to 16v lv8811g and lv8814j ha ve a wide operation voltage range. lv8811 and lv8814j have different lower vcc limit in comparison with the lv8813 to support larger fans. 10 alignment d uty cycle 6% - >5% - > 20% - >15% 50% - >25% lv8813g and lv8814j ha ve stronger alignment to secure the start - up of large - size fans. 20 alignment time 0.8ms 1.0s lv8813g and lv8814j ha ve longer alignment time to secure the start - up of large - size fans. 10 , 20 , 23 , 25 lock detection time 0.33s 0.77s lv8813g and lv8814j ha ve longer detection time to prevent false lock detection on large - size fans at the start - up. 10, 23, 25 lock - stop release time 5.8s 5.4s this characteristic is different due to a different lock detection time. 23, 25 lock/release time ratio 1:5 1:3 package type tssop20j ssop20 tssop20j has the exposed - pad on back. ssop20 don ? t have exposed - pad. foot pattern is same. 34, 35 pin function discription pin no. pin name description 1 vo v - phase output pin 2 uo u - phase output pin 3 rf inverter power supply and motor current sense resistor pin 4 rfs motor current sense 5 vcc power supply pin 6 reg internal regulat or output pin 7 ph1 lead - angle adjustment pin 1 8 ph2 lead - angle adjustment pin 2 9 pwm speed reference i nput pwm p in 10 fg motor speed feedback o utput pin 11 in1 h all sensor input pin 1 12 hb hall sensor bias o utput pin 13 in2 h all s ensor input pin 2 14 mds m inimum output pwm duty cycle setting pin 15 vth speed reference input dc voltage pin 16 cpwm pwm clock frequency control pin 17 sgnd system g round pin 18 wo w - phase output pin 19 nc no connection 20 pgnd power ground pin
lv8811g , lv8813g , lv8814j www. onsemi.com 9 maximum ratings (note 1) parameter symbol value unit maximum supply voltage (note2) vcc max 20 v maximum output voltage (note 3 ) vout max 20 v maximum output current (note 3 , note4 ) iout max 2.0 a reg pin maximum load current ireg max 20 m a hb pin maximum load current ihb max 10 m a pwm pin maximum input voltage vpwm max 6 v fg pin maximum voltage vfg max 17 v input pins maximum voltage (note 5 ) (note 6 ) 3.6 v allowable power dissipation (note 7 ) pd max 2. 5 w storage temperature t stg ? 55 to 150 oc junction temperature t j max 150 oc moisture sensitivity level (msl) (note 8 ) msl 3 - lead temperatu re soldering pb - free versions (3 0sec or less) (note 9 ) t sld 2 55 oc esd human body model : hbm (note10) esd hbm 2000 v 1. stresses exceeding those listed in the maximum rating table may damage the device. if any of these limits are exceeded, devic e functionality should not be assumed, damage may occur and reliability may be affected. 2. v cc supply pins are v cc (5pin), rf (3pin), and rfs (4pin). 3. motor power supply pins are uo (2pin), vo (1pin), and wo (18pin). 4. iout max is the peak value of the motor supply current. 5. input pins are ph1 (7pin), ph2 (8pin), in1 (11pin), in2 (13pin), mds (14pin), vth (15pin), and cpwm (16pin). 6. pin : symbol ph1:vph1 max , ph2:vph2 max , in1:vin1 max , in2:vin2 max , mds:vmds max , vth:vvth max , cpwm:vcpwm max 7. specified circuit board : 5 7 . 0 mm 5 7 . 0 mm 1. 6 mm, glass epoxy 2 - layer board. it has 1 oz copper traces on top and bottom of the board. please refer to thermal test conditions of page 32. 8. moisture sensitivity level (msl): 3 per ipc/jedec standard: j - std - 020a 9. for information, please refer to our soldering and mounting techniques reference manual, solderrm/d http://www.onsemi.com/pub_link/collateral/solderrm - d.pdf 10. esd human body model is based on jedec standard: jesd22 - a114 thermal characteristics parameter symbol condition value unit thermal resistance, junction - to - ambient (note7) r -$ case of the lv8811g and lv8813g 50.0 oc/w case of the lv881 4j 95.0 oc/w thermal resistance, junction - to - case (top) (note7) r -7 case of the lv8811g and lv8813g 15.5 oc/w case of the lv881 4j 35.0 oc/w figure 6 . power dissipation vs ambient temperature characteristic 0 0.4 0.8 1.2 1.6 2 2.4 2.8 - 40 - 20 0 20 40 60 80 100 120 140 allowable power dissipation pdmax - w ambient temperature, ta - ? c
lv8811g , lv8813g , lv8814j www. onsemi.com 10 recommended operating ranges (note 1 1 ) parameter symbol ratings unit vcc supply voltage range at lv8811g and lv8814j (note2) vcc op 3.6 to 16.0 v vcc supply voltage range at lv8813g (note2) 6.0 to 16.0 v pwm input frequency range f pwm 20 to 50 khz pwm input duty cycle range d pwm 0 to 100 % pwm input voltage range v pwm 0 to 5 v in1 input voltage range v in1 0 to v reg v in2 input voltage range v in2 0.3 to 1.8 v con trol input voltage range (note 1 2 ) (note 1 3 ) 0 to v reg v ambient temperature t a ? 40 to 105 oc 11. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recommended operating ranges limits may affect device reliability. 12. control input pins are ph1, ph2, mds, and vth 13. pin : symbol ph1:v ph1 , ph2: v ph2 , mds:v mds , vth:v vth electrical characteristics ta =25oc, vcc op = 12v unless otherwi se noted . (note 1 4 ) parameter symbol condition min typ max unit circuit current supply current icc0 pwm = 3v, cpwm=0v, i o =0a 4.5 7.0 m a protection (note 1 5 ) over current detection voltage vth clm the voltage between vcc - rf 0.162 0.180 0.198 v over voltage detection voltage vth ovp vcc pin, guaranteed by design 19 2 0 v over voltage detection hysteresis ?97+ ovp vcc pin, guaranteed by design 2 v lock detection time t ld case of the lv8811g 0.2 3 0.3 2 0.4 1 s case of the lv8813g and lv8814j 0. 5 5 0.7 6 0.9 7 s lock protection time t l p case of the lv8811g 4. 1 5 5. 68 7. 21 s case of the lv8813g and lv8814j 3. 82 5. 23 6. 6 4 s thermal protection detection temperature t thp guaranteed by design 150 180 ?& thermal protection detection hysteresis ?7 thp guaranteed by design 15 ?& regulator reg pin output voltage v reg 2.7 3.0 3.3 v output uo/vo/wo output resistance rout on i o =0.8a, high - side + low - side 0.5 0.65 fg output (note 1 6 ) fg pin low level output voltage v fgl i fg =5ma 0.3 v fg pin leak current i fglk v fg =16v 1 $ hall bias & hall signal input hb pin output voltage v hb i hb =5ma 1.06 1.18 1.30 v in1/in2 input current i h 1 $ hall signal input hysteresis ?9 h guaranteed by design +/ - 10 mv continued on next page.
lv8811g , lv8813g , lv8814j www. onsemi.com 11 continued from preceding page. parameter symbol condition min typ max unit pwm input pwm pin low level input voltage v pwml 0 0.6 v pwm pin high level input voltage v pwmh 2.3 5.5 v pwm on time t pwmon guaranteed by design 2 00 ns pwm off time t pwmoff guaranteed by design 2 00 ns cpwm input cpwm minimum output ratio (note1 7 ) v cpwml v reg 100 16 18 20 % cpwm maximum output ratio (note1 7 ) v cpwmh v reg 100 65 67 69 % cpwm source current i cpwmso v cpwm =1.3v 17 29 41 cpwm sink current i cpwmsi v cpwm =1.3v - 41 - 29 - 17 $ 14. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwis e noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 15. refer to the protection circuit explanation in the function description . refer to page 23. 16. for fg output pin, it is recommended to connect pull - up resistor between the pin and power supply of the controller. 17. v cpwmh and v cpwml are peak voltage of triangle wave in cpwm pin.
lv8811g, lv8813g , lv8814j www. onsemi.com 12 typical characteristics figure 7 . supply current vs vcc voltage figure 8 . v reg output voltage vs vcc voltage figure 9 . output on resistance vs output current figure 10 . current limiter detection voltage vs vcc voltage figure 11. v reg output voltage vs reg load current figure 12 . fg output voltage vs fg input current
lv8811g, lv8813g , lv8814j www. onsemi.com 13 figure 13 . fg leakage current vs fg input voltage figure 14. v hb output voltage vs hb load current figure 15. pwm threshold voltage vs vcc voltage figure 16. v hb output voltage vs vcc voltage figure 17 . in1/in2 input current vs in1/in2 input voltage figure 18 . cpwm charge/discharge current
lv8811g, lv8813g , lv8814j www. onsemi.com 14 functional description power supply pins (v cc, rf ) rf is output power supply whereas vcc is other circuit supply. the rf pin supplies large current to built - in power mos ftes. ( figure 23) * please re fer to p age . 15 ? motor current sense resistor pin (rf) ? about th e clm sense resistance of rf terminal . gnd pin (sgnd, pgnd) pgnd is power ground whereas sgnd is other circuit ground. since pgnd has to tolerate surge of current, separate it from the sgnd as far away as possible and connect it point - to - point to the ground side of the capacitor (c m ) between power supply and ground . internal 3.0v voltage regulator pin (reg) an internal 3.0v voltage regulator acts a power source for internal logic, oscillator, and protection circuits. when mds and ph1 and ph2 are used, it is recommended that application circuits are made using this output . in addition, the application circuit of vth is same, too. the maximum load current of reg is 10ma. warn not to exceed this. place capacity of 1uf degree and the 0.1uf degre e in the close this pin . ( figure 19) figure 19 . equivalent circuit of reg rotational signal pi n ( fg ) frequency of the fg output represents the motor?s electrical rotational speed (the same rectangular waves as the uo). it is an open drain output. recommen ded pull up resistor value is 1 k to 1 0 k . leave the pin open when not in use. ( figure 20) figure 20 . equivalent circuit of fg motor drive output p ins (uo, vo, wo) these pins are output of built - in three - phase mosfet based inverter that drives the motor. each leg of the inverter is having high side p - mosfet and low side n - mosfet. ( figure 21) figure 21. equivalent circuit of u/v/w hall - s ensor bias output pi n ( hb) the lv811 g , lv8813g , and lv8814 provide a bias regulator output (1.18v typ.) for a hall sensor. it is recommended that this output used only for hall sensor bias. hall - s ensor input pins (in1, in2) differential output signals of the h all sensor are connected to in1 and in2 individually . its polarity is determined by a combination of the number of slot and poles. ( figure 29) i t is recommended to add 0.1uf capacitor between them to filter system noise . topologies , in the case of a hall ic, are shown in figure 30 on page 18. t he topology (including polarity) is also determined by the combination of the number of slot and poles.
lv8811g, lv8813g , lv8814j www. onsemi.com 15 when the pin in1 is connected to the output of the hall ic, the pin in2 must be kept in the middle level of the hall ic power supply voltage. when the pin in2 is connected to the output of the hall ic , the pin in1 must be kept in the middle level of the hall ic power supply voltage. because of the input circuit ( figure 22 ), t he input voltage of in2 must be higher than 0.3v. therefor e , t he resistance ratio must be decided so that in2 voltage is higher than 0.3v. ( figure 30) regarding the polarity of a hall sensor and ic, refer ? rotation direction ? on page 18. figure 22 equivalent circuit of in1, in2 motor current sense resistor pin (rf ) this is also the power supply pin for the built - in power inverter . voltage across the sense resistor represents the motor current and is compared against the internal vth ovc (0.18vtyp.) for setting the over - current lim iter ( clm ). ( figure 23) figure 23 . schematic view of power current route the sense resistor value is calculated as follows. sense resistor [ clm clm for example, to set the c lm current threshold at 1.5a, the sense resistor value is sense resistor = 0. 18 ( typ ) 1.5 res = 0. 12 [ motor current sense pin (rfs) this pin read s voltage across the series sense resistor and compares with internal vth clm . when the measured voltage exceeds vth clm , c lm is triggered and when it falls below vth clm , the lv8811 g, lv88 13g , and lv8814j ex its from the c lm mode . a series rc filter is r ecommend ed to avoid false detection due to switching noise. ( figure 24) figure 24 . schematic view of the clm circuit pgnd rf the serise resistor (sence resistor) the power mos fets u vcc v w ? ? ? ? ? ?v > vth ?
lv8811g, lv8813g , lv8814j www. onsemi.com 16 command input (pwm) this pin reads the d uty cycle of the pwm pulse and controls rotational speed. the pwm input signal level is supported from 2.5v to 5v. the combination with the rotational speed control by dc voltage is impossible. when th e pin is not used, it must be connected to ground . the minimum pulse width is 2 00ns. ( figure 25) figure 25 . equivalent circuit of pwm minimum duty cycle setting pin (mds) the too small duty cycle of the input pwm can be blanked out. the threshold of the min imum duty cycle is configurable. the dc voltage level applied to this pin is converted to this threshold . the voltage is fetched right after the power - on - reset. because the internal conversion circuit works inside reg power ra i l , it is recommended that the m d s voltage is made from v reg . this pin is also used for setting of fg frequency. refer ? parameter setting by constant voltage ? on page 28, and ? setting minimum pwm d uty cycle ? on page 29. lead - angle setting pin (p h1, ph2) lv8811 g, lv8813g , and lv8814j provide the dynamic lead angle adjustment. to match the motor characteristics, the base angle and change ratio with respect to the rotation speed can be configured. the dc voltage level s applied to these pins are converted to the lead angle parameter . the volt age s are fetched right after the power - on- reset. because the internal conversion circuit works inside reg power rail , it is recommended that the ph1 and ph2 voltage s are made from v reg . refer ? parameter setting by co nstant voltage ? on page 28 , and ? setting lead angle ? on page 30. pwm frequency settin g pin (cpwm ) when rotational speed is controlled with the dc voltage, this pin is used. the frequency of the triangle wave which th e pin generates at external capacity can be changed. the frequency of this triangle wave equals frequency of the pwm control that the outp ut works. the relations between the external capacitor and frequency are shown in the next equation . pwm frequency f pwm [hz] is, f pwm cpwmsi o cpwmh ? cpwml pwm where, i cpwmsi o cpwmso ? cpwmsi charge/discharge current v cpwmh : 2.01[v] (typ.) upper peak voltage of cpwm triangle waveform. 67% of 3v v reg v cpwml : 0.54[v ] ( typ.) lower peak voltage of cpwm triangle waveform. 18% of 3v v reg for example, the capacitance of cpwm, to make the pwm frequency 30 khz , can be determ ined by the followings 30k = 29u 2. 94 c pwm pwm ? c pwm decides output pwm frequency. thus, this value must choose appropriately. the range from 220pf to 330pf is recommended. cpwm is represented c 5 in the application circuit diagram, figure 4 on page 5 . the combination with the rotational speed control by pwm is impossible. when this pin is not used, it must be connected to gnd. refer ? pwm duty cycle control by analog voltage ? on page 26. ( figure 26) figure 26 . equivalent circuit of cpwm
lv8811g, lv8813g , lv8814j www. onsemi.com 17 rotational control p in by dc voltage (v th ) this pin reads the input dc voltage and controls rotational speed. the vth voltage is compared with the cpwm triangle wave with an internal comparator and generates pwm pulse and controls rotational speed with frequency and d uty cycle of this pulse. if the external control signal is the pulse type, it should be flattening by the filter and be shifted to suitable level. the external circuit example is shown in figure 4 . vth input level flatten by the filter is calculated in the following equation. v vth = v reg ? r 15 + r 16 r a ? r 14 r 16 r a r b d pwm 100 ? where r a = r 14 + r 15 + r 16 r b = r 14 + r 15 v vth = vth input level this calculation is justified by the condition that rds of mn1 << r 16 . so, a large value of resistor should be selected to r 16 . for example, w hen the input pwm duty cycle is set in 5 0%, can be determined by follows. v vth = 3 [ v ] ( 0. 698 ? 0. 498 50 [ % ] 100 ) v vth = 1. 35 [ v ] where r 14 =7.5[k ] , r 15 =30[k ], r 16 =62[k ] the cut - off frequency fc by c 4 and r 18 is calculated in the following equation. f c = 1 2? ? 4 ? 18 the actual value of c 4 or r 18 is better to select more than 50 times the above calculation value to be flatten thoroughly. furthermore, it is better to do it by the value of c 3 because of the effect of input impedance at vth pin. if the external control signal is the dc type, i t inputs into direct vth pin . however, it is recommended that the filter (c 4 and r 18 ) is kept because rid of the influence of the noise. the cpwm amplitude is decided by vref. thus, vth recommends that it is made from v reg . the combination with the rotati onal speed control by pwm is impossible. when th e pin is not used, it must be open. refer ? pwm duty cycle control by analog voltage ? on page 26 . ( figure 27) figure 27. equivalent circuit of vth nc pin (nc) this pin is not connection to the internal circuit.
lv8811g, lv8813g , lv8814j www. onsemi.com 18 detailed descriptio n as for all numerical value used in this description, the design value or the typical value is used. rotation direction the motor type can be categorized into two groups as 3s2p and 3s4p. (s: slot, p: pole). the 3s2p group contains 3s2p, 6s4p and 12s8p, for instance, and 3s4p g roups contains 3s4p, 6s8p and 9s12p. the rotate direction of 3s2p group is cw, that of 3s4p group is ccw. the direction can be changed by exchanging connection between u and w, in the case where the hall sensor is between u coil and w coil. ( figure 28) figure 28 . schematic diagram of motor hall output polarity also needs to be set with the type of sp motors. it is shown in figure 29, figure 30 figure 29. hall element use connection figure 30 . hall ic use connection 13 in 2 12 hb 11 in1 hall - + 13 in2 12 hb 11 in1 hall - + 3s2p 6s4p 12s8p 3 s 4 p 6 s 8 p 9 s 12 p 6 reg 13 in2 12 hb 11 in1 open hall ic vdd vss 6 reg 13 in 2 12 hb 11 in1 hall ic vdd vss 3s2p 6s4p 12s8p 3s4p 6s8p 9s12p open 3s2p 6s4p 12s8p 3s4p 6s8p 9s12p
lv8811g, lv8813g , lv8814j www. onsemi.com 19 device start - up the lv8811 g , lv8813g , and lv8814j will start driving, when the pwm signal is input at the pwmin pin after a power supply is turned on. commutation the commutation timing is determined with respect to the one hall sensor or hall - ic signal , while conventional sensor - based bldc motor drivers need three sensors. output waveform the output pwm duty cycle is modulated so that the phase - to - phase voltage waveform is sinusoidal. two phases are driven with pwm, while the other phase sunk to ground. it can handle the rotational speed u p to the 2 50hz of fg frequency (electrical cycle) . however, for high speed case, it depends on motor mechanical parameters . low speed side recommends the rotational speed down to the 30hz of fg frequency . a wave pat tern example is shown in figure 31. the amplitude of current waveform is controlle d with input pwm duty cycle while the sinusoidal waveform is kept. figure 32. normal rotation (output pin) l l l h h h l l l h h h in1 0% max uo vo wo fg hall comparator in1 + in1 - u - out fg current of u - out input pwm duty - cycle 50 % input pwm duty - cycle 100 % figure 31 . timing chart example: normal rotation
lv8811g, lv8813g , lv8814j www. onsemi.com 20 detail of the rotor start position align ment after detecting input pwm, the motor - rotor is aligned to the start position. the s tart position alignment is independent on the input pwm d uty cycle, and applies the preset duty cycle described below . [lv8811g] the output pwm duty cycle sequence for the rotor alignment consists of the three steps. alignment duty cycle 1st: 6% , 2nd: 5% , 3rd: 20% [lv8813g , lv8814j ] the output pwm duty cycle sequence for the rotor alignment consists of the single step. alignment duty cycle 50% ( figure 33) figure 33 . timing chart example: alignment duty cycle rotation start - up and soft - start after the adjustment of the start positi on, the output duty - cycle begin from 15% (lv8811g) or 25% (lv8813g , lv8814j ). t he motor starts to rotate in sinusoidal drives, increasing output duty cycle (increment slope is 26 [ %/s ] ) t ill the output duty cycle reaches the target duty cycle . in case the input pwm duty cycl e is under 20%, the output duty cycle decreases to the target duty cycle (decrement slope is 26[%/s]) after reaching 20%. after 32 fg pulses the lead angle increases to the target lead angle (tuned from ph1/ph2) by 1 degree steps at every fg edge. ( figure 34) figure 34 . timing chart example: positioning and soft start 0% 6% 20 % output duty [%] time 30khz output frequency [khz] input frequency [khz] input duty [%] 60% 30khz 5% 50% 800 ms 1s 25% 15% lv8811g alignment time lv 8813 g and lv 8814 j alignment time lv8813g, lv8814j lv8811g 60ms time 0.8s / 1.0s 0 lead angle [deg] = 1 [deg/fg] target lead angle fg count = 32 lead angle adjusting positioning drive sinusoidal drive output duty [%] (duty was set more than 20%) output duty [%] (duty was set less than 20%) 20% alignment term alignment term target duty( > 20% ) target duty( < 20% ) = 26[%/sec] = - 26[%/sec] lv 8813 g lv8811g lv8813g lv8811g 20% lv 8814 j lv8814j
lv8811g, lv8813g , lv8814j www. onsemi.com 21 figure 35. alignment and soft start (case of the lv8811g) pwm fg u out current of u - out input pwm duty - cycle 18 % input pwm duty - cycle 50 %
lv8811g, lv8813g , lv8814j www. onsemi.com 22 duty cycle decreasin g and stop when input pwm duty cycle is changed f rom high to low , the output duty cycle decreases gradually to low with the decrement slope of 26[%/s] . the t arget duty cycle is always updated at positive edge of fg. ( figure 36) figure 36 . timing chart example: when pwm duty cycle changed (80% - > 20% - > 60% - > 0%) figure 37 . input duty cycle changing (case of the lv8811g) time [sec] output duty [%] alignment term 0 0.8s / 1.0s 20% 80 % 60% input duty [%] 80% 20% 60% 0% 80% 20% 60% = 26[%/sec] 80 % 80% 20% 20% input pwm duty target pwm duty fg pulse lv8813g lv8811g lv8814j pwm fg u - out current of u - out 80% 5 0% 0% 2 0%
lv8811g, lv8813g , lv8814j www. onsemi.com 23 output frequency when input pwm duty cycle is 100%, the output frequency is 66khz generated from the internal oscillator. when input pwm duty cycle is changed from 100% to low (e.g. 50% with 30khz), output frequency is changed from 66khz to input pwm frequency (this case is 30khz). when input pwm duty cycle is changed to 100% again, output frequency will remain last input frequency (this case is 30k hz ) . ( figure 38) figure 38 . timing chart example: output frequency changing protections when thp (thermal protection) or clm (current limiter) is detected, the output duty cycle decreases to the m inimum duty cycle rapidly. after exiting the protection mode, the output duty cycle increases with 26 [ %/s ] slope. whe n ovp (over v oltage p rotection) or lvd (low v oltage d etection) signal is d etected, all outputs are turned off. after ovp and lvd are released, outputs are turned on . ( figure 39) when the current limiter is detected, the o utput duty cycle may be restricted before achieving target duty cycle . the output duty cycle decreases immediately by the current limiter. the current limiter is releas e, because the output duty cycle decreases . herewith, the output duty cycle increases to the target duty cycle. and the current limiter is detect ed again, and the output duty cycle decreases. on/off of the current limiter is repeated, and the output duty cycle is limited . when the pwm input changes to low duty cycle that release clm, the output duty cycle decreases gradually with normal slope rate of 26[%/s]. ( figure 40) when c urrent limiter activates with 100% input duty cycle , the o utput duty cycle is restricted before achieving target duty cycle (100%). when the pwm input changes from less than low duty cycle, the output duty cycle decreases to the input duty cycle immediately without slope rate. ( figure 41) the level of c urrent l imiter is adjustable using the value of rf resistor. the value of rf re sistor should be set higher than the current drawn at 100% input duty cycle. lock detection and lock protection [lv8811g] it takes 5. 6 8 s for l ock protection time . l ock start time is 1.12 s . this equals to the total of l ock detect time and the alignment time. the protection - start time ratio is approx. 1 :5 . output under lock protect ion is in hi - z state. ( figure 43) [lv8813g , lv8814j ] the lock protection beh avior is same as lv8811g. however, the release time and re start time are changed as follows: lock protection time: 5.23s lock start time: 1.7 6 s protection - start ratio: approx. 1 :3 ( figure 44) w hen the lock start time, heat is generated that b ecause ic turn ed on electricity to the motor . on the other, w hen the lock protection time, radiated heat that b ecause ic turn ed off electricity to the motor . figure 39 . timing chart example: protections 20% 50% 100% output duty [%] time 66 khz (initial freq) output frequency [khz] input frequency [khz] input duty [%] alignment term 100 % 50% 100% (dc) (dc) 30khz 30khz 100% 50% 100% 30khz 15 % 25% lv8811g lv8813g lv8814j 20% 50% 80% output duty [%] time 80% 20% 50% pwm off pwm off input duty thp or clm ovp lvd
lv8811g, lv8813g , lv8814j www. onsemi.com 24 figure 41 . timing chart example: current limiter at input duty cycle 100% figure 42 . inputting 100% with and without clm (case of the lv8811g) 20% 80 % output duty [%] time 30khz output frequency [khz] input frequency [khz] input duty [%] alignment term 80% 50% 30khz 30khz 30 khz target 80% 50% clm (current limitter) *in the case of lv8811g 15 % limit duty 25% lv8811g lv8813g, lv8814j 20% 100 % output duty [%] time 66khz (initial) output frequency [khz] input frequency [khz] input duty [%] alignment term 100% 50% (dc) 30khz 30 khz target 100% 50% 15% limit duty 25% clm (current limitter) *in the case of lv8811g lv8811g lv8813g, lv8814j fg current of u - out pwm u - out 100% duty 100% duty 50% duty 50% duty clm on at pwm duty - cycle 100% clm o ff at pwm duty - cycle 100% figure 40 . timing chart example: normal current limiter (e.g. input duty cycle 80% - > 50%)
lv8811g, lv8813g , lv8814j www. onsemi.com 25 figure 43 . timing chart example: lock protection for lv8811g figure 44. timing chart example: lock protection for lv8813g and lv8814j figure 45. lock protection (case of the lv8811g) alignment drive lock detect lock protect alignment drive lock detect time [sec] 0.80s 0.80s 0.32s 0.32s 5.68s lock start time lock protection time 1.12sec 5.68sec lock start time 1.12sec ( hi - z state ) lock start time : lock protection time = 1.12 : 5.68 1: 5 (protection - start ratio) alignment drive lock detect lock protect alignment drive lock detect time [sec] 1.00s 1.00s 0.76s 0.76s 5.23s lock start time lock protection time 1.76sec 5.23sec lock start time 1.76sec ( hi - z state ) lock start time : lock protection time = 1.76 : 5.23 1: 3 (protection - start ratio) pwm fg u - out current of u - out lock protect alignment & lock detect re - start lock protect
lv8811g, lv8813g , lv8814j www. onsemi.com 26 pwm duty cycle control by analog vo ltage the d uty cycle of pwm output is determined by comparison of cpwm oscillation and dc level which is input to vth pin. when cpwm level is lower than vth, the pwm output applies the voltage to the coil from the power supply. when cpwm level is higher than vth, the pwm out put is switched to the current circulation state with self - induction of the coil. the dc level of vth can control between v reg 18% and v reg 67% . but t he pwm pulse width must not make less than 2 00ns. t he pulse width of 0s is accepted. ( figure 46) figure 46 . pwm duty cycle control by cpwm and the vth voltage the relations of v vth and output pwm duty cycle are clculated by following equation. v vth = v cpwmh ? ( v cpwmh ? v cpwml ) d out 100 where d out = output pwm duty cycle for example, w hen the output pwm duty cycle is set in 30%, it can be determined by follows. v vth = 2 . 01 [ v ] ? ( 2 . 01 [ v ] ? 0 . 54 [ v ] ) 30 [ % ] 100 = 1 . 569 [ v ] w hen the output pwm duty cycle is set in 100%, it is recommended to set the vth input level lower than v cpwml . in addition, w hen the output pwm duty cycle is set in 0%, it is recommended to set the vth input level higher than v cpwmh . the input range of vth is calculated in the following equation. ( figure 47 ) h = t t h vth control range [ v ] = 0 . 18v reg + h ~ 0 . 67 v reg ? h where, h = v cpwmh [ v ] ? v cpwml [ v ] t = ( v cpwmh ? v cpwml ) [ v ] c 5 [ pf ] i cpwmsi / o [ a ] t = 200ns 2 = 100ns *c 5 is the cpwm pin external capacity. refer to page. 5 and 17 for example, when 3 3 0[pf] is used for cpwm capacity, can be determined by followings h = 0 . 1 [ us ] 16. 73[ us ] 1 . 47 [ v ] = 8 . 79 [ mv ] from the above - mentioned result, the range of the vth input voltage is ? full speed 0.18v reg or less than , ? rotational speed control 0.18v reg + 8 . 79 [ m v] to 0.67v reg -8 . 79[ m v], ? motor stop 0.67v reg or more than vth cpwm pwm controllable duty by vht input fixed duty by mds setting v reg x 67% v reg x 18% the pulse width 200ns and more. the pulse width 200ns and more.
lv8811g, lv8813g , lv8814j www. onsemi.com 27 figure 47 . reference of the calculation of the vth input range t h cpwm vth pwm 2t' h' pulse width ( 200 ns and more) ?abc ~ ?ade bc : de = ac : ae t : t' = h : h' t h ? t' h' ? a b c d e h t t h = ' '
lv8811g, lv8813g , lv8814j www. onsemi.com 28 parameter setting by constant voltage ph1, ph2 and mds can be set by the external dc voltage levels . ph1 and ph2 are used for setting the lead angle . mds is for setting m inimum duty cycle. the input span of these pin s is 0 to 3v (v reg ). the full scale is divided by 64 steps, thus the resolution is 47mv /step . excluding t he low est 3 steps and the high est 2 steps, the dc voltage is translated to the parameters linearly. hence, the linear setting range is 0.141v to 2.906v. the voltage within the lowest 3 steps ( 0 to 0.141v ) selects the default value. as for the highest 2 steps is below . mds ? lowest 3 steps are fg cycle 1 electrical , and default set ting for mds . ? highest 2 steps is fg cycle 2 electrical , and default set ting for mds . p h1/ph2 ? highest 2 steps is prohibit. ( figure 48) figure 48 . pin - set ph1, ph2 and mds 0v 1.0v 2.0v 3.0v 1/3 vreg 2/3 vreg vreg vph1[v] vph2[v] vmds[v] 64 step 3 step 2 step default setup prohibit 0.141v 3/64 x vreg max set 2.906v 62/64 x vreg 15deg - 30deg 0deg 15deg 30deg 60deg 0.15deg/hz 0.15deg/hz 0deg/hz 0.3deg/hz 14% 8% 4% 6% 14% 34% 26% 48% 2% 20% 8% 3% 4% 1% 6% 6% 28% 42% 6% 6% adjustable range (60 step) ph1 lead angle axis intercepts[deg] ph2 lead angle gradients[deg/hz] (lead angle vs fg frequency) mds minimum input duty [%] enable disable hys 8% 14 fg freq 1/2 6%
lv8811g, lv8813g , lv8814j www. onsemi.com 29 setting minimum pwm d uty cycle when the input pwm duty cycle is less than the minimum duty cycle, which is set by mds pin voltage, the output duty cycle becomes 0%. a nd, this threshold has hysteresis. in the meantime, mds pin is also used for the fg frequ ency setting. ( figure 49, figure 50) v mds range [v] 0 ~ 0.141 0.141 ~ 0.282 0.282 ~ 0.752 0.752 ~ 2.906 2.906 ~ 3.0 m inimum input duty cycle hysteresis [%] 6 1 4 6 6 m inimum input duty cycle for enable [%] 14 15 . 9 ? ??? + 1 . 763 14 m inimum input duty cycle for disale [%] 8 15 . 9 ? ??? + 1 . 763 ? ? ?? figure 49 . example setting minimum pwm duty cycle (case of default setting) figure 50 . example setting minimum pwm duty cycle (case of 1/2 v reg setting) vmds[v] (4%) (48%) output duty 100% 48% 14% 8% 0% 0v default setting disable 8% enable 14% 141mv 2.906v ajustment range vreg(3.0v) vmds 47k mds vmds 47k vreg * fg cycle = 2 electrical mds vmds 47k vreg 47k r mds_ a r mds_ b vmds = vreg * (r mds_ b / (r mds_ a + r mds_ b)) = 1/2 vreg output duty 100% 48% 20% 26% vmds[v] 0% 0v vreg(3.0v) disable 20% enable 26% 141mv 2.906v ajustment range (4%) (48%) mds
lv8811g, lv8813g , lv8814j www. onsemi.com 30 setting lead angle ph1 and ph2 pin determine the optimum lead angle for a specific speed range. ph1 provides lead angle at the low speed, the ph2 pin provides lead angle slant for speed (fg frequency). both pin s become the initial value in gnd. ( figure 51, figure 52, figure 53) the lead angle p (typ.) is determined by the following equatio n. ? = ? ? ?? + ? ? = 0. 108 1 ? ?? 2 ? 0. 015 ? = 32 . 54 ? ?? 1 ? 34 . 58 where ? ?? is fg frequency [ hz ] when v ph1 and ? ?? 2 = 0 ? = 0. 15 [deg/hz] ? = 15 [ deg ] note: the equations above are based on the ideal case as a reference for the user application design. it must be readjusted by an experimental confirmation with the actual movement and the motor to be used. figure 51 . example setting lead angle (case of default setting) figure 52 . example setting lead angle (case of 1/3v reg and 4/5v reg setting) default setup 30hz(450rpm) 20deg 100hz(3000rpm) 30deg 200hz(6000rpm) 45deg ph1 vph1 47k ph2 vph2 47k default setup lead angle a x ffg + b a : tuned from vph2 b : tuned from vph1 vph1[v] 120deg 60deg 15deg - 30deg 0v vreg default vph1 = 0v vph2 = 0v 400hz 20step fg frequency[hz] 1/2 vreg lead angle [deg] (100hz, 30deg) max vph1 = max vph2 = max vph1 = min vph2 = max vph1 = max vph2 = min min vph1 = min vph2 = min adjustment setup 30hz(450rpm) 0deg 100hz(3000rpm) 22deg 200hz(6000rpm) 47deg vph1 = vreg * (r ph1 _b / (r ph1 _a + r ph1 _b)) = 1/3 vreg vph2 = vreg * (r ph2 _b / (r ph2 _a + r ph2 _b)) = 4/5 vreg 120deg 60deg 0deg - 30deg 0v vreg 400hz 20step fg frequency[hz] 1/3 vreg lead angle [deg] (100hz, 22deg) vph1 = max vph2 = min fixed from vph2= 4/5 x vreg vph1 = max vph2 = max vph1 15k vreg 30k r ph1_ a r ph1_ b ph2 vph2 43k vreg 11k r ph2_ a r ph2_ b vph1 = 1v vph2 = 2.4v vph1 = min vph2 = min
lv8811g, lv8813g , lv8814j www. onsemi.com 31 sinusoidal pwm signals are generated from 1 - hall signal, handling the lead angle parameters. figure 53. timing chart example: lead angle efficiency and sinusoidal waveform can be optimized by changing the voltage levels of ph1 and ph2. first, adjust ph1 in low speed (low pwm duty cycle ) such as 20%. in the examples below, vph1 = ~1.5v is the best case for efficiency and the shape of sinusoidal wave. after optimizing vph1, adjust vph2 adjusted in high speed (high pwm duty cycle ) such as 100%. ( figure 54) figure 54 . relations of the lead angle and rotational speed, waveform and efficiency (case of the lv8811g) l l l h h h l l l h h h in1 0% max uo vo wo fg hall comparator max 0% 0% max in1 + in1 - lead angle pwm fg u - out current of u - out pwm fg u - out current of u - out input pwm duty - cycle 20 % , vph1 = 0.3v input pwm duty - cycle 20 % , vph1 = 1.5v input pwm duty - cycle 100 % , vph2 = 2.8v
lv8811g, lv8813g , lv8814j www. onsemi.com 32 pcb guidelines vcc and ground routi ng make sure to short - circuit vcc line externally by a low impedance route on one side of pcb. as high current flows into pgnd, connect it to gnd through a low impedance route. the capacitance connected between the vcc pin and the opposite ground is to stabilize the battery. make sure to connect an electrolytic capacitor with capacitance value of about 10uf ( 4 . 7 uf or greater) to eliminate low frequency noise. also, to eliminate h igh frequency noise, connect a capacitor of superior frequency characteristics, with capacitance value of about 0.1uf and make sure that the capacitor is connected as close to the pin as possible. allow enough room in the design so the impact of pwm drive and kick - back does not affect other components. especially, when the coil inductance is large and/or the coil resistance is small, current ripple will rise so it is necessary to use a high - capacity capacitor with superior frequency characteristics. please note that if the battery voltage rises due to the impact of the coil kick - back as a result of the use of diode for preventing the break down caused by reverse connection, it is necessary to either increase the capacitance value or place z ener diode betwee n the battery and the ground so that the voltage does not exceed absolute maximum voltage. when the electrolytic capacitor cannot be used, add the resistor with the value of about 1 (r20) and a ceramic capacitor with the capacitor value of about 10f (c20 ) in series for the alternative use. when the battery line is extended, (20 - 30 cm to 2 - 3 m), the battery voltage may overshoot when the power is supplied due to the impact of the routing of the inductance. make sure that the voltage does not exceed the abs olute maximum standard voltage when the power supply turns on. these capacitance values are just for reference, so the confirm ation with the actual application is essential to de termine the value s appropriately. exposed pad the exposed pad is connected to the frame of the lv8 8 1 1g , lv8813g , and lv8814j . therefore, do not connect it to anywhere else other than ground. if gnd and pgnd are in the same plane, connect the exposed pad to the ground plane. else, if gnd and pgnd are s eparated, connect the exposed pad to gnd. rf routing power current (output current) flows through the rf line. make sure to short - circuit the line from vcc through rf as well as vcc. the rf resistance must choose the enough power rating . nc pin utilizati on nc pins are not connected internally inside the lv8 8 1 1g , lv8813g , and lv8814j . if the nc pin has to be connected to another pin for the development of the pcb board, make sure to assign the pin using wires of stable voltage and current with lower impedance value. motor driver output pins since the pin s have to tolerate surge of current, make sure that the wires are thick and short enough when designing the pcb board. thermal test conditi ons size: 5 7 . 0 mm 5 7 . 0 mm 1. 6 mm ( double la yer pcb) material: glass epoxy copper wiring density: l1 = 80% / l 2 = 85% recommendation the thermal data provided is for the thermal test condition where 9 5 % or more of the exposed die pad is soldered. it is recommended to derate critical rating parameters for a safe design. electrical parameters that are recommended to be derated are operating voltage, operating current, junction temperature, and device power dissipation. the recommended derating for a safe design is as shown below: maximum 80% or less for operating voltage maximum 80% or less for operating current maximum 80% or less for junction temperature check solder joints and ver ify reliability of solder joint s for critical areas such as exposed die pad, power pins and grounds. any void or deterioration, if observed, in solder joint of these critical areas parts, may cause deterioration in thermal conduction and that may lead to thermal destruction of the device.
lv8811g, lv8813g , lv8814j www. onsemi.com 33 l1 : copper wiring pattern diagram (top ) l 2 : copper wiring pattern diagram (bottom) figure 55 . pattern diagram of top and bottom layer
lv8811g, lv8813g , lv8814j www. onsemi.com 34 package dimension s figure 56 lv8811g and lv8813g package
lv8811g, lv8813g , lv8814j www. onsemi.com 35 figure 57 lv8814j package
lv8811g, lv8813g , lv8814j www. onsemi.com 36 on semiconductor and the on semiconductor logo are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries in the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectua l property . a listin g o f o n semiconductor? s product/paten t coverag e ma y b e accesse d a t www.onsemi.com/site/pdf/patent-marking.pdf . o n semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.

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